Anuj Pathania

Latest

• Anuj Pathania successfully completed the intensive Senior Teaching Qualification (STQ) programme.
• Efficient Multimodal Spatial Reasoning via Dynamic and Asymmetric Routing
• The Multi-Partner Project paper 'Collaborative Innovation in 3D VLSI Reliability (COIN-3D)' will be presented at DATE 2026.
• Anuj Pathania was interviewed by the South Korean CBS Nocut news channel about the 'AI Paradox: Convenience Addiction, Accelerated Climate Crisis'.
• The paper 'MaCP: Minimal yet Mighty Adaptation via Hierarchical Cosine Projection' received the Best Theme Paper Award at ACL 2025!
• The paper 'MaCP: Minimal yet Mighty Adaptation via Hierarchical Cosine Projection' was accepted at ACL 2025.
• The paper 'Para-Pipe: Exploiting Hierarchical Operator Parallelism of ML Computational Graphs on SoCs' was accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).
• ISSE
• Empowering Sustainability: Energy Labeling of Digital Services Using Simulation
• Energy-Efficient QoS-Aware Scheduling for S-NUCA Many-Cores
• SSH: Sparse Spectrum Adaptation via Discrete Hartley Transformation
• The paper 'Empowering Sustainability: Energy Labeling of Digital Services Using Simulation' was accepted as a short paper at CCGrid 2025.
• The paper 'Energy-Efficient QoS-Aware Scheduling for S-NUCA Many-Cores' was accepted at ISQED 2025.
• Compact SER Models for Line-Source-Induced Charge Collection Using Model Order Reduction
• Para-Pipe: Exploiting Hierarchical Operator Parallelism of ML Computational Graphs on SoCs
• Para-Pipe: Exploiting Hierarchical Operator Parallelism of ML Computational Graphs on SoCs
• COIN-3D
• ARM-CO-UP: ARM COoperative Utilization of Processors
• The paper 'Analyzing Per-Application Energy Consumption in a Multi-Application Computing Continuum' was accepted at IEEE FMEC '24.
• Analyzing Per-Application Energy Consumption in a Multi-Application Computing Continuum
• PiQi: Partially Quantized DNN Inference on HMPSoCs
• The paper 'Lifetime Estimation for Core-Failure Resilient Multi-Core Processors' was accepted for IEEE MCSoC '23.
• The paper '3D-TTP: Efficient Transient Temperature-Aware Power Budgeting for 3D-Stacked Processor-Memory Systems' was accepted for publication at IEEE ISVLSI '23.
• The patent 'Power management for multicore processors' has been successfully published under number EP 4 152 124.
• Edge AI
• Thermals
• The chapter 'Pipelined CNN Inference on Heterogeneous Multi-Processor System-on-Chip' was accepted for the book on Embedded Machine Learning for Cyber Physical, IoT, and Edge Computing (Springer).
• The paper 'CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5 D, and 3D Processor-Memory System' was accepted for ACM Transactions on Architecture and Code (TACO).
• HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction
• T-TSP
• The paper 'HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction' was accepted for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
• CoMeT
• HotSniper
• EnergyLabels
• HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction
• The paper 'ChordMap: Automated Mapping of Streaming Applications onto CGRA' was accepted for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
• ChordMap: Automated Mapping of Streaming Applications onto CGRA
• CoMeT: An Integrated Interval Thermal Simulation Toolchain for 2D, 2.5D, and 3D Processor-Memory Systems
• Neural Network-Based Performance Prediction for Task Migration on S-NUCA Many-Cores
• Power-Efficient Heterogeneous Many-Core Design With NCFET Technology
• The paper 'HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction' was accepted for DATE 2021.